1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to data communication systems employing analog and digital components.
2. Description of Related Art
Data communication systems have been long been under development. One particular design direction has been the movement towards always faster operating devices within the communication system. Particularly within receivers employed within digital communication systems, the rate at which an analog to digital converter (ADC) can properly sample a received analog signal is of some critical consideration. In order to enable regeneration/re-synthesize a digitally sampled signal into the analog signal that has been actually received and sampled by the ADC, then the sampling rate of the ADC needs to be clocked at a frequency at least twice the highest frequency component in the analog received signal. This will enable that the entirety of the received signal, at least up the “highest frequency component” of interest will be able to perform accurate regeneration of the received signal.
Many data communication systems also employ signal processing that involves both an in-phase (I) component and a quadrature (Q) component carried on a common signal. These two components are typically extracted using some type of interface that extracts the I and Q streams and converts them down to a baseband frequency for analog to digital conversion using two separate ADCs, one for the I stream and one for the Q stream.
ADCs can prove to be very real estate consumptive components within semiconductor devices. Given their oftentimes large real estate consumption, the ADCs within a semiconductor device often also prove to be large consumers of power as well. In the typical implementation of employing two distinct ADCs, one for the I stream and one for the Q stream, the real estate consumption of the ADCs can prove very large with respect to the total available area within an entire semiconductor device. In addition, any gradient or differential characteristics (mismatches) in the processing/manufacturing of the semiconductor device will potentially lead to different operating characteristics of the two ADCs. These differences may generate deleterious effects in the digital data that are generated by sampling the incoming I and Q analog data streams. This mismatch between the ADCs that perform the I and Q stream sampling may require some other corrective signal processing operations to accommodate these inconsistencies. These mismatches may become even more accentuated and problematic when employing higher order modulation schemes; the soft and hard bit decisions are even more blurred when the I and Q stream ADCs have mismatches between them.
Virtually any communication system having receivers that perform quadrature sampling of incoming data will employ the two ADC design, one ADC for the I stream and the Q stream. All of these potential deleterious effects may be realized in such a receiver device that employs this conventional design as described above.
Further limitations and disadvantages of conventional and traditional systems will become apparent through comparison of such systems with the invention as set forth in the remainder of the present application with reference to the drawings.